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Espressif Systems /ESP32-S2 /UHCI0 /DMA_IN_STATUS

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Interpret as DMA_IN_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_FULL)IN_FULL 0 (IN_EMPTY)IN_EMPTY 0RX_ERR_CAUSE

Description

UHCI data-input status register

Fields

IN_FULL

Data-input FIFO full signal.
IN_EMPTY

Data-input FIFO empty signal.
RX_ERR_CAUSE

This register indicates the error type when DMA has received a packet with error. 3’b001: Checksum error in the HCI packet; 3’b010: Sequence number error in the HCI packet; 3’b011: CRC bit error in the HCI packet; 3’b100: 0xC0 is found but the received HCI packet is not end; 3’b101: 0xC0 is not found when the HCI packet has been received; 3’b110: CRC check error.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data